(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create insulator filled, shallow trench, isolation regions.
(2) Description of the Prior Art
The use of localized oxidation of silicon, (LOCOS), as a method for creating isolation regions, for semiconductor devices, has been replaced by insulator filled, shallow trench regions. The increased cost and performance objectives, of the semiconductor industry, are difficult to achieve using a LOCOS, or a field oxide, (FOX), isolation technology. FOX procedures, accomplished via thermal oxidation of exposed regions of the semiconductor substrate, to be used as isolation regions, normally result in "birds beak" phenomena, or unwanted growth of silicon dioxide, under the edges of a oxidation resistant mask, used to protect the device region from the FOX procedure. Therefore to maintain the desired dimensions for the active device region, an increase in the design dimensions of the active device region has to be included to accommodate the unwanted "birds beak" formation. The use of larger than desired design dimensions, result in larger than desired semiconductor chips, resulting in less chips being obtained from a specific size, semiconductor substrate, thus increasing the processing costs for a specific semiconductor chip.
The use of shallow trench isolation, (STI), wherein a shallow trench is formed in a semiconductor substrate, followed by filling the shallow trench with a chemically vapor deposited, (CVD), insulator layer, allows the designed, active device region to remain intact, without the "birds beak" encroachment presented with LOCOS type isolation formation. The use of STI procedures, however do inherent problems, in the form of device leakage, and yield phenomena. For example the trench profile, needed to maintain design groundrules, and needed to allow adequate insulator fill, has to be created using either isotropic or anisotropic, reactive ion etching, (RIE), procedures. These RIE procedure can result in bombardment damage to silicon regions, exposed in the shallow trench. These defects, near the surface of the shallow trench, do not allow a uniform, silicon oxide liner layer, to be thermally grown. The silicon oxide liner, used to separate silicon regions from the CVD insulator fill, in addition to not being uniform in thickness, as a result of the RIE damage, can also be defective, in terms of low breakdown strength, as a result of being grown from a silicon surface that was exposed to the RIE, or plasma bombardment. In addition the defects in these silicon regions, when interfaced with active device regions, such as source/drain regions, of a metal oxide semiconductor field effect transistor, (MOSFET), device, can result in unwanted junction leakage, and possible yield loss.
This invention will describe a process for creating a shallow trench, in a semiconductor region, however subjecting the etched trench to a specific, high temperature hydrogen anneal, prior to the formation of the trench liner layer. This high temperature hydrogen anneal allows repair of the silicon surface, previously damaged by RIE bombardment. The silicon surface is also more accessible when using hydrogen anneals, than when using nitrogen, or other inert annealing ambients, due to the ability of hydrogen to reduce native oxide, on the silicon surface, and thus directly treat the damaged silicon surface. In addition the use of the high temperature hydrogen anneal, results in the formation of a denuded zone, a region of decreased oxygen in silicon, near the STI surface, allowing subsequent junction formation near the STI region, to be realized with reduced junction leakage. Prior art, such as Fahey et al, in U.S. Pat. No. 5,447,884, describe a process for STI formation, however without the critical high temperature anneal procedure, taught in this present invention, and needed for optimum junction quality.